Compact Video Controller:

   CVC is a verilog IP designed for imaging graphical information to SVGA monitor in security, gaming, ... applications and synthesized on Xilinx Spartan-IIE FPGA.

• Resolution - 800x600 pixels
• 16 Bit color per pixel
• Vertical scanning - 72 Hz

Time Slot Interchange Digital Switch:

   The TDM Switch core is a non-blocking digital switch that has a capacity of 256 x 256 channels at 2.048 Mb/s. The serial input streams can have a bit rate of 2.048Mb/s and are arranged in 125 us wide frames, witch contain 32 channels respectively. The data rates on input and output streams are indentical.

• 256 x 256 channel non-blocking switching at 2.048 Mb/s
• Accept 8 serial data streams of 2.048 Mb/s
• Per-stream frame delay offset programming
• Connection memory block programming
• Microprocessor Interface

   This IP core is synthesized for XILINX SPARTAN-II series FPGA, fit at xc2s50-6tq144 device and the post place & route simulation model simulate with Cadence NC-SIM simulator.

Multi-Speed Time Slot Interchange Digital Switch:

   The Multi-Speed TDM Switch core is a non-blocking digital switch that has a capacity of 256 x 256 channels at 2.048 Mb/s and 256 x 256 channels at 16.384 Mb/s.

• 512 x 512 channel non-blocking switching at 2.048 Mb/s and 16.384 Mb/s
• Input clock 32.768 MHz
• Frame Sync 125us
• Accept 8 serial data stream of 2.048 Mb/s and one serial data stream of 16.384 Mb/s
• Per-stream frame delay offset programming
• Connection memory block programming
• Microprocessor Interface

   This IP core is synthesized for XILINX SPARTAN-IIE series FPGA, fit in XC2S50E-6TQ144 device and the post place & route simulation model simulate with Cadense NC-SIM simulator.

   The UART is a fully functional, synthesizable, universal asynchronous receiver-transmitter verilog core. The receiver and the transmitter operate independently, each can be selectively disabled for synthesis. Due to its modularity and configurability, the UART core is ideal for system-on-chip or as embedded processor peripherals.